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<h1>Serial Parallel Interface Peripheral</h1>
<null><a name="SPI"></a><b>SPI</b> <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_SPI">AT91S_SPI</a>)</font></i><b>  0xFFFE0000 </b><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_BASE_SPI">AT91C_BASE_SPI</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>5</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_ID_SPI">AT91C_ID_SPI</a>)</font></i></font></td><td><font size="-1">Serial Peripheral Interface</font></td></tr>
</null></table><br><table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1"><b>Signal</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Symbol</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>PIO controller</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b>
</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>NPCS0</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA11_NPCS0   ">AT91C_PA11_NPCS0   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 11</font></td><td><font size="-1">SPI Peripheral Chip Select 0</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>MOSI</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA13_MOSI    ">AT91C_PA13_MOSI    </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 13</font></td><td><font size="-1">SPI Master Out Slave</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>NPCS1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA31_NPCS1   ">AT91C_PA31_NPCS1   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 31</font></td><td><font size="-1">SPI Peripheral Chip Select 1</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>NPCS1</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA9_NPCS1   ">AT91C_PA9_NPCS1   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: B Bit: 9</font></td><td><font size="-1">SPI Peripheral Chip Select 1</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>NPCS2</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA30_NPCS2   ">AT91C_PA30_NPCS2   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: B Bit: 30</font></td><td><font size="-1">SPI Peripheral Chip Select 2</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>NPCS2</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA10_NPCS2   ">AT91C_PA10_NPCS2   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: B Bit: 10</font></td><td><font size="-1">SPI Peripheral Chip Select 2</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>NPCS3</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA22_NPCS3   ">AT91C_PA22_NPCS3   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: B Bit: 22</font></td><td><font size="-1">SPI Peripheral Chip Select 3</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>NPCS3</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA3_NPCS3   ">AT91C_PA3_NPCS3   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: B Bit: 3</font></td><td><font size="-1">SPI Peripheral Chip Select 3</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>NPCS3</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA5_NPCS3   ">AT91C_PA5_NPCS3   </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: B Bit: 5</font></td><td><font size="-1">SPI Peripheral Chip Select 3</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>MISO</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA12_MISO    ">AT91C_PA12_MISO    </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 12</font></td><td><font size="-1">SPI Master In Slave</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>SPCK</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA14_SPCK    ">AT91C_PA14_SPCK    </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 14</font></td><td><font size="-1">SPI Serial Clock</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_CfgPMC">AT91F_SPI_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for SPI</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_CfgPIO">AT91F_SPI_CfgPIO</a></b></font></td><td><font size="-1">Configure PIO controllers to drive SPI signals</font></td></tr>
</null></table><br><br></null><a name="SPI"></a><h2>SPI Software API <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_SPI">AT91S_SPI</a>)</font></i></h2>
<a name="SPI"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SPI.html#SPI_CR">SPI_CR</a></font></td><td><font size="-1">Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SPI.html#SPI_MR">SPI_MR</a></font></td><td><font size="-1">Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x8</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SPI.html#SPI_RDR">SPI_RDR</a></font></td><td><font size="-1">Receive Data Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SPI.html#SPI_TDR">SPI_TDR</a></font></td><td><font size="-1">Transmit Data Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SPI.html#SPI_SR">SPI_SR</a></font></td><td><font size="-1">Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SPI.html#SPI_IER">SPI_IER</a></font></td><td><font size="-1">Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x18</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SPI.html#SPI_IDR">SPI_IDR</a></font></td><td><font size="-1">Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x1C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SPI.html#SPI_IMR">SPI_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x30</b></font></td><td><font size="-1">SPI_CSR[4] (<a href="AT91SAM7S256_SPI.html#SPI_CSR">SPI_CSR</a>)</font></td><td><font size="-1">Chip Select Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x100</b></font></td><td><font size="-1">SPI_RPR (<a href="AT91SAM7S256_PDC.html#PDC_RPR">PDC_RPR</a>)</font></td><td><font size="-1">Receive Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x104</b></font></td><td><font size="-1">SPI_RCR (<a href="AT91SAM7S256_PDC.html#PDC_RCR">PDC_RCR</a>)</font></td><td><font size="-1">Receive Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x108</b></font></td><td><font size="-1">SPI_TPR (<a href="AT91SAM7S256_PDC.html#PDC_TPR">PDC_TPR</a>)</font></td><td><font size="-1">Transmit Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10C</b></font></td><td><font size="-1">SPI_TCR (<a href="AT91SAM7S256_PDC.html#PDC_TCR">PDC_TCR</a>)</font></td><td><font size="-1">Transmit Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x110</b></font></td><td><font size="-1">SPI_RNPR (<a href="AT91SAM7S256_PDC.html#PDC_RNPR">PDC_RNPR</a>)</font></td><td><font size="-1">Receive Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x114</b></font></td><td><font size="-1">SPI_RNCR (<a href="AT91SAM7S256_PDC.html#PDC_RNCR">PDC_RNCR</a>)</font></td><td><font size="-1">Receive Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x118</b></font></td><td><font size="-1">SPI_TNPR (<a href="AT91SAM7S256_PDC.html#PDC_TNPR">PDC_TNPR</a>)</font></td><td><font size="-1">Transmit Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x11C</b></font></td><td><font size="-1">SPI_TNCR (<a href="AT91SAM7S256_PDC.html#PDC_TNCR">PDC_TNCR</a>)</font></td><td><font size="-1">Transmit Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x120</b></font></td><td><font size="-1">SPI_PTCR (<a href="AT91SAM7S256_PDC.html#PDC_PTCR">PDC_PTCR</a>)</font></td><td><font size="-1">PDC Transfer Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x124</b></font></td><td><font size="-1">SPI_PTSR (<a href="AT91SAM7S256_PDC.html#PDC_PTSR">PDC_PTSR</a>)</font></td><td><font size="-1">PDC Transfer Status Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_Reset">AT91F_SPI_Reset</a></b></font></td><td><font size="-1">Reset the SPI controller</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_Close">AT91F_SPI_Close</a></b></font></td><td><font size="-1">Close SPI: disable IT disable transfert, close PDC</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_Disable">AT91F_SPI_Disable</a></b></font></td><td><font size="-1">Disable the SPI controller</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_Enable">AT91F_SPI_Enable</a></b></font></td><td><font size="-1">Enable the SPI controller</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_SendFrame">AT91F_SPI_SendFrame</a></b></font></td><td><font size="-1">Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_CfgMode">AT91F_SPI_CfgMode</a></b></font></td><td><font size="-1">Enable the SPI controller</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_GetChar">AT91F_SPI_GetChar</a></b></font></td><td><font size="-1">Receive a character,does not check if a character is available</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_PutChar">AT91F_SPI_PutChar</a></b></font></td><td><font size="-1">Send a character,does not check if ready to send</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_DisableIt">AT91F_SPI_DisableIt</a></b></font></td><td><font size="-1">Disable SPI interrupt</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_GetInterruptMaskStatus">AT91F_SPI_GetInterruptMaskStatus</a></b></font></td><td><font size="-1">Return SPI Interrupt Mask Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_IsInterruptMasked">AT91F_SPI_IsInterruptMasked</a></b></font></td><td><font size="-1">Test if SPI Interrupt is Masked </font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_ReceiveFrame">AT91F_SPI_ReceiveFrame</a></b></font></td><td><font size="-1">Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_CfgCs">AT91F_SPI_CfgCs</a></b></font></td><td><font size="-1">Configure SPI chip select register</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_EnableIt">AT91F_SPI_EnableIt</a></b></font></td><td><font size="-1">Enable SPI interrupt</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SPI_CfgPCS">AT91F_SPI_CfgPCS</a></b></font></td><td><font size="-1">Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected</font></td></tr>
</null></table></null><h2>SPI Register Description</h2>
<null><a name="SPI_CR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_CR  <i>Control Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_CR">AT91C_SPI_CR</a></i> 0xFFFE0000</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_SPIEN"></a><b>SPI_SPIEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_SPIEN">AT91C_SPI_SPIEN</a></font></td><td><b>SPI Enable</b><br>0 = No effect.<br>1 = Enables the SPI to transfer and receive data.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_SPIDIS"></a><b>SPI_SPIDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_SPIDIS">AT91C_SPI_SPIDIS</a></font></td><td><b>SPI Disable</b><br>0 = No effect.<br>1 = Disables the SPI.<br>All pins are set in input mode and no data is received or transmitted.<br>If a transfer is in progress, the transfer is finished before the SPI is disabled.<br>If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_SWRST"></a><b>SPI_SWRST</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_SWRST">AT91C_SPI_SWRST</a></font></td><td><b>SPI Software reset</b><br>0 = No effect.<br>1 = Resets the SPI.<br>A software triggered hardware reset of the SPI interface is performed.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="SPI_LASTXFER"></a><b>SPI_LASTXFER</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_LASTXFER">AT91C_SPI_LASTXFER</a></font></td><td><b>SPI Last Transfer</b><br>0 = No effect.<br>1 = Deassert the NPCS after all transfers occured. Useful when CSAAT is set.</td></tr>
</null></table>
<a name="SPI_MR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_MR  <i>Mode Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_MR">AT91C_SPI_MR</a></i> 0xFFFE0004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_MSTR"></a><b>SPI_MSTR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_MSTR">AT91C_SPI_MSTR</a></font></td><td><b>Master/Slave Mode</b><br>0 = SPI is in Slave mode.<br>1 = SPI is in Master mode.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_PS"></a><b>SPI_PS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_PS">AT91C_SPI_PS</a></font></td><td><b>Peripheral Select</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SPI_PS_FIXED"></a><b>SPI_PS_FIXED</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_PS_FIXED">AT91C_SPI_PS_FIXED</a></font></td><td><br>Fixed Peripheral Select</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SPI_PS_VARIABLE"></a><b>SPI_PS_VARIABLE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_PS_VARIABLE">AT91C_SPI_PS_VARIABLE</a></font></td><td><br>Variable Peripheral Select</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_PCSDEC"></a><b>SPI_PCSDEC</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_PCSDEC">AT91C_SPI_PCSDEC</a></font></td><td><b>Chip Select Decode</b><br>0 = The chip selects are directly connected to a peripheral device.<br>1 = The four chip select lines are connected to a 4- to 16-bit decoder.<br>When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16- bit decoder.<br>The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules:<br>	SPI_CSR0 defines peripheral chip select signals 0 to 3.<br>	SPI_CSR1 defines peripheral chip select signals 4 to 7.<br>	SPI_CSR2 defines peripheral chip select signals 8 to 11.<br>	SPI_CSR3 defines peripheral chip select signals 12 to 15 (1) .<br>Note: 1. The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration to be defined by each chip select register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_FDIV"></a><b>SPI_FDIV</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_FDIV">AT91C_SPI_FDIV</a></font></td><td><b>Clock Selection</b><br>0 = SPI Master Clock equals MCK<br>1 = SPI Master Clock equals MCK/N. Product dependancy</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_MODFDIS"></a><b>SPI_MODFDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_MODFDIS">AT91C_SPI_MODFDIS</a></font></td><td><b>Mode Fault Detection</b><br>0 = Mode Fault Detection is enabled<br>1 = Mode Fault Detection is disabled</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_LLB"></a><b>SPI_LLB</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_LLB">AT91C_SPI_LLB</a></font></td><td><b>Clock Selection</b><br>0 = Local loopback path disabled<br>1 = Local loopback path enabled<br>LLB controls the local loopback on the data serializer for testing in master mode only.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SPI_PCS"></a><b>SPI_PCS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_PCS">AT91C_SPI_PCS</a></font></td><td><b>Peripheral Chip Select</b><br>This field is only used if Fixed Peripheral Select is active (PS = 0).<br>	If PCSDEC=0:<br>		PCS = xxx0 NPCS[3:0] = 1110<br>		PCS = xx01 NPCS[3:0] = 1101<br>		PCS = x011 NPCS[3:0] = 1011<br>		PCS = 0111 NPCS[3:0] = 0111<br>		PCS = 1111 forbidden (no peripheral is selected)<br>		(x = don&#146;t care)<br>	If PCSDEC=1: NPCS[3:0] output signals = PCS</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="SPI_DLYBCS"></a><b>SPI_DLYBCS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_DLYBCS">AT91C_SPI_DLYBCS</a></font></td><td><b>Delay Between Chip Selects</b><br>This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times.<br>If DLYBCS is less than or equal to six, six SPI Master Clock periods will be inserted by default.<br>Otherwise, the following equation determines the delay:<br>	Delay_ Between_Chip_Selects = DLYBCS / MCK</td></tr>
</null></table>
<a name="SPI_RDR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_RDR  <i>Receive Data Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_RDR">AT91C_SPI_RDR</a></i> 0xFFFE0008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="SPI_RD"></a><b>SPI_RD</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RD">AT91C_SPI_RD</a></font></td><td><b>Receive Data</b><br>Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SPI_RPCS"></a><b>SPI_RPCS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RPCS">AT91C_SPI_RPCS</a></font></td><td><b>Peripheral Chip Select Status</b><br>In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.</td></tr>
</null></table>
<a name="SPI_TDR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_TDR  <i>Transmit Data Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_TDR">AT91C_SPI_TDR</a></i> 0xFFFE000C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="SPI_TD"></a><b>SPI_TD</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TD">AT91C_SPI_TD</a></font></td><td><b>Transmit Data</b><br>Data which is to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be writ-ten to the transmit data register in a right-justified format.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SPI_TPCS"></a><b>SPI_TPCS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TPCS">AT91C_SPI_TPCS</a></font></td><td><b>Peripheral Chip Select Status</b><br>This field is only used if Variable Peripheral Select is active (PS = 1) and if the SPI is in Master Mode.<br>	If PCSDEC = 0:<br>		PCS = xxx0 NPCS[3:0] = 1110<br>		PCS = xx01 NPCS[3:0] = 1101<br>		PCS = x011 NPCS[3:0] = 1011<br>		PCS = 0111 NPCS[3:0] = 0111<br>		PCS = 1111 forbidden (no peripheral is selected)<br>		(x = don&#146;t care)<br>	If PCSDEC = 1:<br>		NPCS[3:0] output signals = PCS</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="SPI_LASTXFER"></a><b>SPI_LASTXFER</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_LASTXFER">AT91C_SPI_LASTXFER</a></font></td><td><b>SPI Last Transfer</b><br>0 = No effect.<br>1 = Deassert the NPCS after all transfers occured. Useful when CSAAT is set.</td></tr>
</null></table>
<a name="SPI_SR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_SR">AT91C_SPI_SR</a></i> 0xFFFE0010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_RDRF"></a><b>SPI_RDRF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RDRF">AT91C_SPI_RDRF</a></font></td><td><b>Receive Data Register Full</b><br>0 = No data has been received since the last read of SPI_RDR<br>1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_TDRE"></a><b>SPI_TDRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TDRE">AT91C_SPI_TDRE</a></font></td><td><b>Transmit Data Register Empty</b><br>0 = Data has been written to SPI_TDR and not yet transferred to the serializer.<br>1 = The last data written in the Transmit Data Register has been transferred in the serializer.<br>TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_MODF"></a><b>SPI_MODF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_MODF">AT91C_SPI_MODF</a></font></td><td><b>Mode Fault Error</b><br>0 = No Mode Fault has been detected since the last read of SPI_SR.<br>1 = A Mode Fault occurred since the last read of the SPI_SR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_OVRES"></a><b>SPI_OVRES</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_OVRES">AT91C_SPI_OVRES</a></font></td><td><b>Overrun Error Status</b><br>0 = No overrun has been detected since the last read of SPI_SR.<br>1 = An overrun has occurred since the last read of SPI_SR.<br>An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_ENDRX"></a><b>SPI_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_ENDRX">AT91C_SPI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SPI_ENDTX"></a><b>SPI_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_ENDTX">AT91C_SPI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_TXBUFE"></a><b>SPI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TXBUFE">AT91C_SPI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SPI_NSSR"></a><b>SPI_NSSR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_NSSR">AT91C_SPI_NSSR</a></font></td><td><b>NSSR Interrupt</b><br>0 = No rising edge detected on NSS pin since last read.<br>1 = A rising edge occured on NSS pin since last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SPI_TXEMPTY"></a><b>SPI_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TXEMPTY">AT91C_SPI_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>As soon as a data is written in the SPI_TDR.<br>The SPI_TDR register and internal shifter are empty.<br>If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="SPI_SPIENS"></a><b>SPI_SPIENS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_SPIENS">AT91C_SPI_SPIENS</a></font></td><td><b>Enable Status</b><br>0 = SPI is disabled.<br>1 = SPI is enabled.</td></tr>
</null></table>
<a name="SPI_IER"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_IER">AT91C_SPI_IER</a></i> 0xFFFE0014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_RDRF"></a><b>SPI_RDRF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RDRF">AT91C_SPI_RDRF</a></font></td><td><b>Receive Data Register Full</b><br>0 = No data has been received since the last read of SPI_RDR<br>1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_TDRE"></a><b>SPI_TDRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TDRE">AT91C_SPI_TDRE</a></font></td><td><b>Transmit Data Register Empty</b><br>0 = Data has been written to SPI_TDR and not yet transferred to the serializer.<br>1 = The last data written in the Transmit Data Register has been transferred in the serializer.<br>TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_MODF"></a><b>SPI_MODF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_MODF">AT91C_SPI_MODF</a></font></td><td><b>Mode Fault Error</b><br>0 = No Mode Fault has been detected since the last read of SPI_SR.<br>1 = A Mode Fault occurred since the last read of the SPI_SR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_OVRES"></a><b>SPI_OVRES</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_OVRES">AT91C_SPI_OVRES</a></font></td><td><b>Overrun Error Status</b><br>0 = No overrun has been detected since the last read of SPI_SR.<br>1 = An overrun has occurred since the last read of SPI_SR.<br>An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_ENDRX"></a><b>SPI_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_ENDRX">AT91C_SPI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SPI_ENDTX"></a><b>SPI_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_ENDTX">AT91C_SPI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_TXBUFE"></a><b>SPI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TXBUFE">AT91C_SPI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SPI_NSSR"></a><b>SPI_NSSR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_NSSR">AT91C_SPI_NSSR</a></font></td><td><b>NSSR Interrupt</b><br>0 = No rising edge detected on NSS pin since last read.<br>1 = A rising edge occured on NSS pin since last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SPI_TXEMPTY"></a><b>SPI_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TXEMPTY">AT91C_SPI_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>As soon as a data is written in the SPI_TDR.<br>The SPI_TDR register and internal shifter are empty.<br>If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr>
</null></table>
<a name="SPI_IDR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_IDR">AT91C_SPI_IDR</a></i> 0xFFFE0018</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_RDRF"></a><b>SPI_RDRF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RDRF">AT91C_SPI_RDRF</a></font></td><td><b>Receive Data Register Full</b><br>0 = No data has been received since the last read of SPI_RDR<br>1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_TDRE"></a><b>SPI_TDRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TDRE">AT91C_SPI_TDRE</a></font></td><td><b>Transmit Data Register Empty</b><br>0 = Data has been written to SPI_TDR and not yet transferred to the serializer.<br>1 = The last data written in the Transmit Data Register has been transferred in the serializer.<br>TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_MODF"></a><b>SPI_MODF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_MODF">AT91C_SPI_MODF</a></font></td><td><b>Mode Fault Error</b><br>0 = No Mode Fault has been detected since the last read of SPI_SR.<br>1 = A Mode Fault occurred since the last read of the SPI_SR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_OVRES"></a><b>SPI_OVRES</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_OVRES">AT91C_SPI_OVRES</a></font></td><td><b>Overrun Error Status</b><br>0 = No overrun has been detected since the last read of SPI_SR.<br>1 = An overrun has occurred since the last read of SPI_SR.<br>An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_ENDRX"></a><b>SPI_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_ENDRX">AT91C_SPI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SPI_ENDTX"></a><b>SPI_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_ENDTX">AT91C_SPI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_TXBUFE"></a><b>SPI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TXBUFE">AT91C_SPI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SPI_NSSR"></a><b>SPI_NSSR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_NSSR">AT91C_SPI_NSSR</a></font></td><td><b>NSSR Interrupt</b><br>0 = No rising edge detected on NSS pin since last read.<br>1 = A rising edge occured on NSS pin since last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SPI_TXEMPTY"></a><b>SPI_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TXEMPTY">AT91C_SPI_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>As soon as a data is written in the SPI_TDR.<br>The SPI_TDR register and internal shifter are empty.<br>If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr>
</null></table>
<a name="SPI_IMR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_IMR">AT91C_SPI_IMR</a></i> 0xFFFE001C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_RDRF"></a><b>SPI_RDRF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RDRF">AT91C_SPI_RDRF</a></font></td><td><b>Receive Data Register Full</b><br>0 = No data has been received since the last read of SPI_RDR<br>1= Data has been received and the received data has been transferred from the serializer to SPI_RDR since the lastread of SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_TDRE"></a><b>SPI_TDRE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TDRE">AT91C_SPI_TDRE</a></font></td><td><b>Transmit Data Register Empty</b><br>0 = Data has been written to SPI_TDR and not yet transferred to the serializer.<br>1 = The last data written in the Transmit Data Register has been transferred in the serializer.<br>TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SPI_MODF"></a><b>SPI_MODF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_MODF">AT91C_SPI_MODF</a></font></td><td><b>Mode Fault Error</b><br>0 = No Mode Fault has been detected since the last read of SPI_SR.<br>1 = A Mode Fault occurred since the last read of the SPI_SR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_OVRES"></a><b>SPI_OVRES</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_OVRES">AT91C_SPI_OVRES</a></font></td><td><b>Overrun Error Status</b><br>0 = No overrun has been detected since the last read of SPI_SR.<br>1 = An overrun has occurred since the last read of SPI_SR.<br>An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SPI_ENDRX"></a><b>SPI_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_ENDRX">AT91C_SPI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SPI_ENDTX"></a><b>SPI_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_ENDTX">AT91C_SPI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SPI_RXBUFF"></a><b>SPI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_RXBUFF">AT91C_SPI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SPI_TXBUFE"></a><b>SPI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TXBUFE">AT91C_SPI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SPI_NSSR"></a><b>SPI_NSSR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_NSSR">AT91C_SPI_NSSR</a></font></td><td><b>NSSR Interrupt</b><br>0 = No rising edge detected on NSS pin since last read.<br>1 = A rising edge occured on NSS pin since last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SPI_TXEMPTY"></a><b>SPI_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_TXEMPTY">AT91C_SPI_TXEMPTY</a></font></td><td><b>TXEMPTY Interrupt</b><br>As soon as a data is written in the SPI_TDR.<br>The SPI_TDR register and internal shifter are empty.<br>If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.</td></tr>
</null></table>
<a name="SPI_CSR"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SPI_CSR  <i>Chip Select Register</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="AT91SAM7S256_h.html#AT91C_SPI_CSR">AT91C_SPI_CSR</a></i> 0xFFFE0030</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SPI_CPOL"></a><b>SPI_CPOL</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_CPOL">AT91C_SPI_CPOL</a></font></td><td><b>Clock Polarity</b><br>0 = The inactive state value of SPCK is logic level zero.<br>1 = The inactive state value of SPCK is logic level one.<br>CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce a desired clock/data relationship between master and slave devices.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SPI_NCPHA"></a><b>SPI_NCPHA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_NCPHA">AT91C_SPI_NCPHA</a></font></td><td><b>Clock Phase</b><br>0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.<br>1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.<br><br>NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SPI_CSAAT"></a><b>SPI_CSAAT</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_CSAAT">AT91C_SPI_CSAAT</a></font></td><td><b>Chip Select Active After Transfer</b><br>0 = The PCS Line raises at soon as the last transfer is achieved.<br>1 = The PCS does not raise after the last transfer is acheived. It remains active until a new transfer is requested on a different chip select.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7..4</td><td align="CENTER"><a name="SPI_BITS"></a><b>SPI_BITS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS">AT91C_SPI_BITS</a></font></td><td><b>Bits Per Transfer</b><br>The BITS field determines the number of data bits transferred.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SPI_BITS_8"></a><b>SPI_BITS_8</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_8">AT91C_SPI_BITS_8</a></font></td><td><br>8 Bits Per transfer</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SPI_BITS_9"></a><b>SPI_BITS_9</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_9">AT91C_SPI_BITS_9</a></font></td><td><br>9 Bits Per transfer</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SPI_BITS_10"></a><b>SPI_BITS_10</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_10">AT91C_SPI_BITS_10</a></font></td><td><br>10 Bits Per transfer</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SPI_BITS_11"></a><b>SPI_BITS_11</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_11">AT91C_SPI_BITS_11</a></font></td><td><br>11 Bits Per transfer</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SPI_BITS_12"></a><b>SPI_BITS_12</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_12">AT91C_SPI_BITS_12</a></font></td><td><br>12 Bits Per transfer</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SPI_BITS_13"></a><b>SPI_BITS_13</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_13">AT91C_SPI_BITS_13</a></font></td><td><br>13 Bits Per transfer</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="SPI_BITS_14"></a><b>SPI_BITS_14</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_14">AT91C_SPI_BITS_14</a></font></td><td><br>14 Bits Per transfer</td></tr>
<tr><td align="CENTER">7</td><td align="CENTER"><a name="SPI_BITS_15"></a><b>SPI_BITS_15</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_15">AT91C_SPI_BITS_15</a></font></td><td><br>15 Bits Per transfer</td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="SPI_BITS_16"></a><b>SPI_BITS_16</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_BITS_16">AT91C_SPI_BITS_16</a></font></td><td><br>16 Bits Per transfer</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..8</td><td align="CENTER"><a name="SPI_SCBR"></a><b>SPI_SCBR</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_SCBR">AT91C_SPI_SCBR</a></font></td><td><b>Serial Clock Baud Rate</b><br>In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the SPI Master Clock(selected between MCK and MCK/32). The baud rate is selected by writing a value from 2 to 255 in the field SCBR. The following equation determines the SPCK baud rate:<br>	SPCK_Baud_Rate = SPI_Master_Clock_frequency /SCBR<br>Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state value. No serial transfers may occur. At reset, baud rate is disabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">23..16</td><td align="CENTER"><a name="SPI_DLYBS"></a><b>SPI_DLYBS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_DLYBS">AT91C_SPI_DLYBS</a></font></td><td><b>Delay Before SPCK</b><br>This field defines the delay from NPCS valid to the first valid SPCK transition.<br>When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.<br>Otherwise, the following equation determines the delay:<br>NPCS_to_SPCK_Delay = DLYBS / MCK</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="SPI_DLYBCT"></a><b>SPI_DLYBCT</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SPI_DLYBCT">AT91C_SPI_DLYBCT</a></font></td><td><b>Delay Between Consecutive Transfers</b><br>This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.<br>When DLYBCT equals zero, a delay of four SPI Master Clock periods are inserted.<br>Otherwise, the following equation determines the delay:<br>Delay_Between_Consecutive_Transfer = (64 * DLYBCT + SCBR) / (2*MCK)</td></tr>
</null></table>
<a name="SPI_PDC"></a><h4><a href="#SPI">SPI</a>: <i><a href="AT91SAM7S256_h.html#AT91S_PDC">AT91S_PDC</a></i> SPI_PDC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>SPI</b> <i><a href="#AT91C_SPI_SPI">AT91C_SPI_SPI</a></i> 0xFFFE0100</font></null></ul></null><hr></html>
